Project Development in XILINX ISE 10.1

bulge out Development in XILINX ISE 10.1Chapter 4VHDL entryA design engineer in electronic industry uses hardware description language to keep pace with the productivity of the competitors. With VHSIC (Very full(prenominal) Speed Integrated Circuits) Hardware comment Language (VHDL) we shadow rapidly describe and synthesize circuits of several thousand gates. In addition VHDL provides the capabilities described as followsPower and flexibilityVHDL has powerful language constructs with which to write succinct mandate description of complex control logic. It also has multiple levels of design description for controlling design implementation. It supports design libraries and creation of reusable components. It provides forge hierarchies to create warning designs. It is one language fort design and subterfuge.Device Independent designVHDL permits to create a design without having to first choose a device enemy implementation. With one design description, we disregard target many device architectures. Without being familiar with it, we can optimize our design for resource or performance. It permits multiple movement of design description.PortabilityVHDL portability permits to simulate the same design description that we have synthesized. Simulating a large design description before synthesizing can save considerable time. As VHDL is a standard, design description can be taken from one simulator to another, one synthesis tool to another one platform to another-means description can be used in multiple jump outs.Benchmarking capabilitiesDeviceindependent design and portability allows benchmarking a design using different device architectures and different synthesis tool. We can take a complete design description and synthesize it, create logic for it, evaluate the results and finally choose the device-a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA) that fits our requirements.ASIC MigrationThe efficiency that VHDL gen erates, allows our product to hit the market quickly if it has been synthesized on a CPLD or FPGA. When production value reaches distract levels, VHDL facilitates the development of Application Specific Integrated Circuit (ASIC). Sometimes, the exact code used with the Programmable Logic Device (PLD) can be used with the ASIC and because VHDL is a unmortgaged language, we can be assured that out ASIC vendor ordain deliver a device with expected functionality.4.1 VHDL DESCRIPTIONIn the search of a standard design and documentation for the Very High Speed Integrated Circuits (VHSIC) program, the United States Department of Defense (DOD) in 1981sponsored a workshop on Hardware Description Languages (HDL) at Woods Hole, Massachusetts. In 1983, the DOD established requirements for a standard VHSIC Hardware Description Language VHDL, its environment and its software was awarded to IBM, Texas Instruments and Intermetrics corporations.VHDL 2.0 was released only after the project was begu n. The language was significantly improved correcting the shortcoming of the earlier versions VHDL 6.0 was released in 1984. VHDL 1078/1164 formally became the IEEE standard Hardware Description Language in 1987.A VHDL design is specify as an entity declaration and as an associated architecture remains. The declaration specifies its interface and is used by architecture bodies of design entities at upper levels of hierarchy. The architecture body describes the operation of a design entity by specifying its interconnection with other design entities structural description, by its behaviour behavioural description, or by a mixture of both. The VHDL language groups, sub programs or design entities by use of packages.For customizing generic descriptions of design entities, configurations are used. VHDL also supports libraries and contains constructs for accessing packages, design entities or configurations from various libraries.4.2 INTRODUCTION TO XILINX ISE 10.1Create a clean Proje ctCreate a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit display board.To create a new project require File upstart Project The New Project champion appears.Type tutorial in the Project Name field.Enter or browse to a location (directory path) for the new project. A tutorial subdirectory iscreated automatically.Verify that HDL is selected from the Top-Level Source Type list.Click bordering to move to the device properties foliate.Fill in the properties in the table as shown belowProduct Category AllFamily Spartan3Device XC3S200Package FT256Speed tier up -4Top-Level Source Type HDLSynthesis Tool XST (VHDL/Verilog)Simulator ISE Simulator (VHDL/Verilog)Preferred Language Verilog (or VHDL)Verify that Enable Enhanced Design Summary is selected.Leave the default value in the remaining fields.When the table is complete, your project properties will look like the following7. Click Next to proceed to the Create New Source window in the New Project Wiz ard. Atthe end of the side by side(p) section, your new project will be complete.Create an HDL SourceIn this section, you will create the top-level HDL file for your design. Determine the language that you wish to use for the tutorial. Then, continue either to the Creating aVHDL Source section below, or skip to the Creating a Verilog Source section.Creating a VHDL SourceCreate a VHDL source file for the project as followsClick the New Source button in the New Project Wizard.Select VHDL Module as the source type.Type in the file name forestall.Verify that the Add to project checkbox is selected.Click Next.Declare the ports for the counter design by filling in the port information as shown below7. Click Next, then Finish in the New Source Wizard Summary dialog box to complete thenew source file template.8. Click Next, then Next, then Finish.The source file containing the entity/architecture pair displays in the Workspace, and the counter displays in the Source tab, as shown belowChe cking the Syntax of the New Counter ModuleWhen the source files are complete, check the syntax of the design to convey errors and typos.Verify that Implementation is selected from the drop-down list in the Sources window.Select the counter design source in the Sources window to display the related processes inthe Processes window.Click the + next to the Synthesize-XST process to expand the process group.Double-click the Check Syntax process. short letter You must correct any errors found in your source files. You can check for errors in theConsole tab of the Transcript window. If you continue without valid syntax, you will not be able to simulate or synthesize your design.5. Close the HDL file.Design SimulationVerifying Functionality using behavioural SimulationCreate a test bench wave form containing gossip stimulus you can use to drift the functionality of the counter module. The test bench waveform is a graphical view of a test bench.Create the test bench waveform as follows1 . Select the counter HDL file in the Sources window.2. Create a new test bench source by selecting Project New Source.3. In the New Source Wizard, select Test Bench Wave Form as the source type, and typeCounter_tbw in the File Name field.4. Click Next.5. The Associated Source page shows that you are associating the test bench waveformwith the source file counter. Click Next.6. The Summary page shows that the source will be added to the project, and it displaysthe source directory, type, and name. Click Finish.7. You engage to set the clock frequency, setup time and output delay times in the Initialize.Timing dialog box before the test bench waveform editing window opens.The requirements for this design are the followingThe counter must operate correctly with an input clock frequency = 25 MHz.The DIRECTION input will be valid 10 ns before the rising contact of CLOCK.The output (COUNT_OUT) must be valid 10 ns after the rising beach of CLOCK.The design requirements correspond with the values below.Fill in the fields in the Initialize Timing dialog box with the following informationClock High Time 20 ns.Clock Low Time 20 ns.Input Setup Time 10 ns.Output Valid Delay 10 ns. countervail 0 ns.Global signal GSR(FPGA).Note When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically. 8. Click Finish to complete the timing initialization.9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the InputSetup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define theinput stimulus.Note For more accurate alignment, you can use the Zoom In and Zoom Out toolbarbuttons.10. Save the waveform.11. In the Sources window, select the Behavioral Simulation view to take heed that the test benchwaveform file is automatically added to your project.12. Close the test bench waveform.Simulating Design FunctionalityVerify that the counter design functions as you expect by performing behavior simulationas follows1. Verify that Behavioral Simulation and counter_tbw are selected in the Sourceswindow.2. In the Processes tab, click the + to expand the Xilinx ISE Simulator process anddouble-click the Simulate Behavioral Model process.The ISE Simulator opens and runs the simulation to the end of the test bench.3. To view your simulation results, select the Simulation tab and zoom in on the transitions.Note You can tailor any rows that start with TX.4. Verify that the counter is counting up and down as expected.5. Close the simulation view. If you are prompted with the following message, You have anactive simulation open. Are you sure you want to close it? click Yes to continue.You have now completed simulation of your design using the ISE Simulator.